Non-Volatile Multi-Context FPGAs Using Hybrid Multiple-Valued/Binary Context Switching Signals

Multi-context (MC) FPGAs have multiple memory bits per configuration bit forming configuration planes for fast switching between contexts. Large amount of memory causes significant overhead in area and power consumption. This paper presents two key technologies. The first is a floating-gate-MOS functional pass gate that merges storage and switching functions area-efficiently. The second is the use of a hybrid multiple-valued/binary context switching signal that eliminates redundancy of a conventional MC-switch with high scalability. The transistor count of the proposed MCswitch is reduced to 7% in comparison with that of a SRAMbased one. Although the FGFP-based MC-switch is compact, it has a large data path delay. Using a ferroelectric-based functional pass-gate, the delay of the proposed MC-switch is same as that of the SRAM-Based one while reducing the transistor count to 86%.